Sets the power options of crystal and PLL clocks, and initiates reset by software
| SW_STALL_APPCPU_C0 | {reg_sw_stall_appcpu_c1[5:0] , reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU |
| SW_STALL_PROCPU_C0 | When RTC_CNTL_REG_SW_STALL_PROCPU_C1 is configured to 0x21, setting this bit to 0x2 stalls the CPU by SW. |
| SW_APPCPU_RST | APP CPU SW reset. (Note, we don’t have APP CPU for ESP32-S2) |
| SW_PROCPU_RST | Set this bit to reset the CPU by SW. |
| BB_I2C_FORCE_PD | Set this bit to FPD BB_I2C. |
| BB_I2C_FORCE_PU | Set this bit to FPU BB_I2C. |
| BBPLL_I2C_FORCE_PD | Set this bit to FPD BB_PLL _I2C. |
| BBPLL_I2C_FORCE_PU | Set this bit to FPU BB_PLL _I2C. |
| BBPLL_FORCE_PD | Set this bit to FPD BB_PLL. |
| BBPLL_FORCE_PU | Set this bit to FPU BB_PLL. |
| XTL_FORCE_PD | Set this bit to FPD the crystal oscillator. |
| XTL_FORCE_PU | Set this bit to FPU the crystal oscillator. |
| XTL_FORCE_ISO | |
| PLL_FORCE_ISO | |
| ANALOG_FORCE_ISO | |
| XTL_FORCE_NOISO | |
| PLL_FORCE_NOISO | |
| ANALOG_FORCE_NOISO | |
| DG_WRAP_FORCE_RST | Set this bit to force reset the digital system in deep-sleep. |
| DG_WRAP_FORCE_NORST | Set this bit to disable force reset to digital system in deep-sleep. |
| SW_SYS_RST | Set this bit to reset the system via SW. |